(1) Field of the Invention
The present invention relates to a method used to create a stacked capacitor structure, for a dynamic random access memory, (DRAM) device.
(2) Description of the Prior Art
Improved device performance and the reduced manufacturing costs of these devices, are major objectives of the semiconductor industry. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate semiconductor memory chips with sub-micron features, or micro-miniaturization. Sub-micron features allow the reduction in performance degrading capacitances and resistances to be realized. In addition the smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller, or sub-micron, features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
One method of maintaining, or increasing STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grain, (HSG), silicon layers. For example Thakur et al, in U.S. Pat. No. 5,656,531, describe a process for forming an HSG silicon layer, on a capacitor storage node structure, however this invention does not provide a surface preparation, applied to the storage node shape, prior to deposition of the amorphous silicon layer used for HSG formation. The absence of a pre-clean, prior to amorphous silicon deposition can result in poor adhesion between the amorphous silicon layer and the storage node shape. Zahurak et al, in U.S. Pat. No. 5,639,685, do show the use of a pre-clean procedure, however this pre-clean step is applied prior to the deposition of the polysilicon layer, used for the storage node shape, not prior to the deposition of the amorphous silicon layers, used for HSG formation. This invention will describe a process for increasing the surface area of a storage node structure, and thus the capacitance of the DRAM capacitor, via the use of an HSG layer on a patterned polysilicon storage node structure. However this invention will feature a pre-clean sequence, used prior to a deposition of a heavily doped amorphous silicon layer, on the patterned polysilicon storage node structure. The use of a heavily doped amorphous layer, prevents silicon migration. In addition native oxide formation, at the interface between HSG and the underlying silicon stack, can lead to HSG peeling. The a pre-clean procedures, followed by the deposition of a heavily doped silicon layer, prior to HSG formation, retards the native oxide growth, thus reducing the risk of peeling, or of poor adhesion of the HSG layer, to the underlying stack. This invention also features a subsequent deposition of a lightly doped, or undoped, amorphous silicon layer, and a subsequent seeding/anneal procedure, performed in situ, in the same furnace used to deposit the heavily doped amorphous silicon layer, resulting in the formation of a roughened HSG surface. In addition this invention will describes a storage node structure, intentionally designed with a narrow width, to accommodate the additional amorphous silicon layers, thus avoiding shorts between rows of tightly packed capacitor structures.